Techniques for integrating a variety of functional devices in a single integrated circuit by using a common sequence of processing steps are well known in the art. A common approach to forming a capacitor in an MOS process is to replicate the MOS gate structure at some other place on the chip. In this structure the substrate is one capacitor plate and a polysilicon plate, formed during the gate poly deposition, forms the other capacitor plate. In this approach the properties of the capacitor dielectric, e.g. the thickness, is limited by the MOS gate dielectric thickness. Moreover, using this procedure the choice of possible circuit configurations is limited. An additional drawback is that an additional substrate contact is generally required. Alternative approaches are known in which capacitors are formed using a three level metal process. In this case a capacitor can be formed that is electrically distinct from the gate, i.e. can be independently designed and interconnected, but an added metal layer is required in the gate-capacitor structure, i.e. the combination gate/capacitor uses three metal layers. By contrast only two metal layers are required to form the capacitor and the gate structures using the process of this invention.